1. Field of the Invention
The present invention is directed to the field of microprocessor control systems and more specifically to the area of a circuit which provides reset signals to the microprocessor upon restoration of power and in the event of program lock up.
2. Background Information
Watchdog timers are commonly used in association with microprocessor control devices. Such timers function to monitor the program operation and provide a reset signal whenever the program locks up (stops running). Watchdog timers are normally combined with other dedicated circuits to ensure that a reset signal is provided to the microprocessor during a power-up period, when operational voltages are first applied. After a sufficient period, following power-up, the reset signal is removed and the microprocessor is allowed to initialize to start its main program and output a corresponding status signal. The watchdog timer circuit monitors the status signal pulse train output from the microprocessor to cause a reset signal to be applied to the microprocessor in the event the pulse train ceases.
Microprocessors (also called microcomputers) conventionally include an initialization subroutine which, after a sufficient time delay to allow all power levels to be stabilized, sets the program counter to a zero count and addresses the location of its read only memory in accordance with the zero count of the program counter. The contents of the read only memory location allows the initialization program to define and establish initial conditions for microprocessor operation. In order to commence the initialization process, the microprocessor requires the appropriate voltage from an associated power supply followed by the predetermined reset signal applied to a dedicated input/output port. Subsequent to the initialization subroutine, the microprocessor begins its main program sequence and provides a status signal in the form of a pulse train that is output on a dedicated port at a predetermined frequency and duty cycle in sequence with the program execution steps performed within the microprocessor. In the event of a program failure due to fluctuating voltages or other transients which cause the program to stop, the status signal pulse train will also stop. The function of the watchdog timer is to then apply a reset signal to the microprocessor and cause the initialization subroutine to run and subsequently start the main program.
U.S. Pat. No. 4,586,179 teaches the use of a watchdog timer circuit that is in combination with a separate source voltage level detector circuit. The two separate functions are gated through a single triggering circuit to provide separate resets to the microprocessor. Upon power-up, the source voltage level detector biases the triggering circuit in such a way as to hold the reset terminal at a low level which corresponds to the RESET signal. When the source voltage level reaches a predetermined value, a first monostable multivibrator in the watchdog timer is triggered and outputs a biasing voltage to the trigger circuit so that the trigger circuit continues to hold the reset level low for a predetermined time period as determined by a RC network that holds the first monostable multivibrator in its unstable state. Subsequently, after the initialization period, the status signal output from the microprocessor is input to a second monostable multivibrator of the watchdog timer circuit. The train of pulses is said to hold the second monostable multivibrator in its unstable state. However, when the status signal ceases, the monostable multivibrator 42 switches to its unstable state and causes the first multivibrator 44 to enter its unstable state for a period of time as determined by the RC network and cause the RESET signal to be input to the microprocessor for that period of time.
The watchdog timer circuit of the '179 patent provides one reset signal for each suspension of status signals from the microprocessor. Therefore, if the first reset signal fails to restart the microprocessor, no further reset signals are generated.
Further improvements to watchdog timers has resulted in the use of a comparator circuit configured as an astable multivibrator with resistive feedback to compare the status signal from the microprocessor with a reference level and to provide the appropriate reset signals.